This invention relates to a line accommodation circuit for use in combination with a cell exchange apparatus in a digital electronic exchange system. It is to be noted throughout the instant specification that the line accommodation circuit is given a wide variety of communication information signals and serves to convert the communication information signal or signals into an asynchronous transfer mode (ATM) cell and to send each ATM cell to the cell exchange apparatus.
In general, such a line accommodation circuit is connected to input and output lines through which the communication information signals are transmitted in the form of an input data signal and an output data signal. Each of the input and the output data signals is transmitted at a low bit rate in comparison with the ATM cell formed in the line accommodation circuit.
Specifically, the line accommodation circuit has a redundancy structure and comprises a pair of function systems one of which acts as an active system and the other of which acts as a backup or a standby system. The active and the standby systems will be often abbreviated to ACT and SBY systems, respectively, and are switched from one to another on occurrence of a fault or the like.
Herein, let the line accommodation circuit be given as the input data signal a synchronous data signal which includes a frame synchronization signal. Under the circumstances, it is assumed that the active system is switched to the standby system with reference to the frame synchronization signal to switch the synchronous data signal from the active system to the standby system. However, the line accommodation circuit does not have structure such that all sections or elements of the line accommodation circuit are synchronously operated. Therefore, a frame loss or a loss of the synchronous data signal often takes place on such a switching operation from the active system to the standby system.
On the other hand, it is assumed that an asynchronous data signal like a packet signal is given as the input data signal to the line accommodation system and is switched from the active system to the standby system. In this case, an input operation of the asynchronous data signal is temporarily interrupted during such a switching operation while received and stored asynchronous data signals should be transferred from the active system to the standby system. With this structure, it takes a long time to transfer the stored asynchronous data signals from the active system to the standby system. As a result, a long time is required for the switching operation. In addition, complexed control operation or procedure should be carried out in the line accommodation circuit.